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NLAST44599 Low Voltage Single Supply Dual DPDT Analog Switch
The NLAST44599 is an advanced CMOS dual-independent DPDT (double pole-double throw) analog switch, fabricated with silicon gate CMOS technology. It achieves high-speed propagation delays and low ON resistances while maintaining CMOS low-power dissipation. This DPDT controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The device has been designed so the ON resistance (RON) is much lower and more linear over input voltage than RON of typical CMOS analog switches. The channel-select input structure provides protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. This input structure helps prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. The NLAST44599 can also be used as a quad 2-to-1 multiplexer- demultiplexer analog switch with two Select pins that each controls two multiplexer-demultiplexers.
http://onsemi.com MARKING DIAGRAMS
16 1
T QFN-16 MN SUFFIX CASE 485G ALYW (TOP VIEW)
* * * * * * * * *
Select Pins Compatible with TTL Levels Channel Select Input Overvoltage Tolerant to 5.5 V Fast Switching and Propagation Speeds Break-Before-Make Circuitry Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C Diode Protection Provided on Channel Select Input Improved Linearity and Lower ON Resistance over Input Voltage Latch-up Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 158 FETs
A L Y W 1 TSSOP-16 DT SUFFIX CASE 948F 16
16 NLAST 4459 ALYW 1
* * Pb-Free Packages are Available
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
Semiconductor Components Industries, LLC, 2005
February, 2005 - Rev. 7
1
Publication Order Number: NLAST44599/D
NLAST44599
QFN-16 PACKAGE
COM A NO A0 NC D1 VCC FUNCTION TABLE Select AB or CD L H ON Channel NC to COM NO to COM
16
15
14
13
12
NC A1 SAB
COM D
1
See TSSOP-16 Switch Configuration
2
11 10
NO D0 SCD
NO B0 COM B
3
NC C1
4
9
COM C
NC B1
GND
NO C0
0 1 2
COM A
0/1
NO A0
1
16
VCC
COM B SELECT CD
2/3 X1
3 0 1 2
COM C NC A1 3 14 COM D COM D ELECT AB 4 13 NO D0
0/1
2/3
3
Figure 2. IEC Logic Symbol
NO B0 5 12 SELECT CD
COM B
6
11
NC C1
NC B1
7
10
COM C
GND
8
9
NO C0
Figure 1. Logic Diagram
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2
U
COM A
2
15
NC D1 U
U
U
U
U
U
U
U
TSSOP-16 PACKAGE
U
U
U
8
SELECT AB X1 NO A0 NC A1 NO B0 NC B1 NO C0 NC C1 NO D0 NC D1
7
6
5
NLAST44599
MAXIMUM RATINGS
Symbol VCC VIS VIN IIK PD TSTG TL TJ MSL FR VESD Positive DC Supply Voltage Analog Input Voltage (VNO or VCOM) Digital Select Input Voltage DC Current, Into or Out of Any Pin Power Dissipation in Still Air Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Moisture Sensitivity Flammability Rating ESD Withstand Voltage Oxygen Index: 30% - 35% Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) QFN-16 TSSOP-16 QFN-16 TSSOP-16 Parameter Value *0.5 to )7.0 *0.5 VIS VCC )0.5 *0.5 VI )7.0 $50 800 450 *65 to )150 260 +150 Level 1 UL-94-VO (0.125 in) 2000 200 1000 $300 80 164 V Unit V V V mA mW C C C
ILATCH-UP qJA
Latch-Up Performance Thermal Resistance
mA C/W
Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 1. Tested to EIA/JESD22-A114-A. 2. Tested to EIA/JESD22-A115-A. 3. Tested to JESD22-C101-A. 4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VIS TA tr, tf DC Supply Voltage Digital Select Input Voltage Analog Input Voltage (NC, NO, COM) Operating Temperature Range Input Rise or Fall Time, SELECT VCC = 3.3 V $ 0.3 V VCC = 5.0 V $ 0.5 V Parameter Min 2.0 GND GND *55 0 0 Max 5.5 5.5 VCC )125 100 20 Unit V V V C ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
Junction Temperature C 80 90 100 110 120 130 140 NORMALIZED FAILURE RATE Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130C TJ = 120C TJ = 100C TJ = 110C TJ = 90C TJ = 80C 100 TIME, YEARS
1 1 10 1000
Figure 3. Failure Rate vs. Time Junction Temperature
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NLAST44599
DC CHARACTERISTICS - Digital Section (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage, Select Inputs Maximum Low-Level Input Voltage, Select Inputs Maximum Input Leakage Current Power Off Leakage Current, Select Inputs Maximum Quiescent Supply Current VIN = 5.5 V or GND VIN = 5.5 V or GND Select and VIS = VCC or GND Condition VCC 3.0 4.5 5.5 3.0 4.5 5.5 5.5 0 5.5 *555C to 255C 2.0 2.0 2.0 0.5 0.8 0.8 $0.2 $10 4.0 t855C 2.0 2.0 2.0 0.5 0.8 0.8 $2.0 $10 4.0 t1255C 2.0 2.0 2.0 0.5 0.8 0.8 $2.0 $10 8.0 Unit V
VIL
V
IIN IOFF ICC
mA mA mA
DC ELECTRICAL CHARACTERISTICS - Analog Section
Guaranteed Limit Symbol RON Parameter Maximum "ON" Resistance (Figures 17 - 23) Condition VIN = VIL or VIH VIS = GND to VCC IINI v 10.0 mA VIN = VIL or VIH IINI v10.0 mA VIS = 1 V, 2 V, 3.5 V VIN = VIL or VIH VNO or VNC = 1.0 VCOM 4.5 V VIN = VIL or VIH VNO 1.0 V or 4.5 V with VNC floating or VNO 1.0 V or 4.5 V with VNO floating VCOM = 1.0 V or 4.5 V VCC 2.5 3.0 4.5 5.5 4.5 *555C to 255C 85 45 30 25 4 t855C 95 50 35 30 4 t1255C 105 55 40 35 5 Unit W
RFLAT (ON) INC(OFF) INO(OFF) ICOM(ON)
ON Resistance Flatness (Figures 17 - 23) NO or NC Off Leakage Current (Figure 9) COM ON Leakage Current (Figure 9)
W
5.5 5.5
1 1
10 10
100 100
nA nA
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NLAST44599
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Guaranteed Maximum Limit VCC Symbol tON Parameter Turn-On Time (Figures 12 and 13) Test Conditions RL = 300 W, CL = 35 pF (Figures 5 and 6) (V) 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 2.5 3.0 4.5 5.5 VIS (V) 2.0 2.0 3.0 3.0 2.0 2.0 3.0 3.0 2.0 2.0 3.0 3.0 *555C to 255C Min 5 5 2 2 1 1 1 1 1 1 1 1 Typ* 23 16 11 9 7 5 4 3 12 11 6 5 Max 35 24 16 14 12 10 6 5 t855C Min 5 5 2 2 1 1 1 1 1 1 1 1 Max 38 27 19 17 15 13 9 8 t1255C Min 5 5 2 2 1 1 1 1 1 1 1 1 Max 41 30 22 20 18 16 12 11 Unit ns
tOFF
Turn-Off Time (Figures 12 and 13)
RL = 300 W, CL = 35 pF (Figures 5 and 6)
ns
tBBM
Minimum Break-Before-Make Time
VIS = 3.0 V (Figure 4) RL = 300 W, CL = 35 pF
ns
*Typical Characteristics are at 25C. Typical @ 25, VCC = 5.0 V CIN CNO or CNC CCOM C(ON) Maximum Input Capacitance, Select Input Analog I/O (Switch Off) Common I/O (Switch Off) Feedthrough (Switch On) 8 10 10 20 pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
VCC Symbol BW Parameter Maximum On-Channel *3 dB Bandwidth or Minimum Frequency Response (Figure 11) Maximum Feedthrough On Loss Condition VIN = 0 dBm VIN centered between VCC and GND (Figure 7) VIN = 0 dBm @ 100 kHz to 50 MHz VIN centered between VCC and GND (Figure 7) f = 100 kHz; VIS = 1 V RMS VIN centered between VCC and GND (Figure 7) VIN = VCC to GND, FIS = 20 kHz tr = tf = 3 ns RIS = 0 W, CL = 1000 pF Q = CL * DVOUT (Figure 8) FIS = 20 Hz to 100 kHz, RL = Rgen = 600 W, CL = 50 pF VIS = 5.0 VPP sine wave f = 100 kHz; VIS = 1 V RMS VIN centered between VCC and GND (Figure 7) V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 5.5 Typical 255C 145 170 175 -3 -3 -3 -93 -93 -93 1.5 3.0 Unit MHz
VONL
dB
VISO
Off-Channel Isolation (Figure 10) Charge Injection Select Input to Common I/O (Figure 15)
dB
Q
pC
THD
Total Harmonic Distortion THD ) Noise (Figure 14) Channel to Channel Crosstalk
% 5.5 5.5 3.0 0.1 dB -90 -90
VCT
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NLAST44599
DUT VCC 0.1 mF 300 W Output VOUT 35 pF Input
VCC GND tBMM 90% Output 90% of VOH
Switch Select Pin GND
Figure 4. tBBM (Time Break-Before-Make)
VCC DUT VCC 0.1 mF Open Output VOUT 300 W 35 pF Output VOL tON tOFF Input 0V VOH 50% 50%
90%
90%
Input
Figure 5. tON/tOFF
VCC DUT Output Open 300 W VOUT 35 pF Input
VCC 50% 0V VOH Output VOL 10% tOFF tON 10% 50%
Input
Figure 6. tON/tOFF
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NLAST44599
50 W Reference Input Output 50 W Generator 50 W DUT Transmitted
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. VISO = Off Channel Isolation = 20 Log VONL = On Channel Loss = 20 Log VOUT VIN for VIN at 100 kHz VOUT for VIN at 100 kHz to 50 MHz VIN
Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 W
Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL
DUT Open Output CL Output VIN
VCC GND
Off VIN
On
Off
DVOUT
Figure 8. Charge Injection: (Q)
100
10
LEAKAGE (nA)
1
0.1
ICOM(ON) ICOM(OFF)
0.01
VCC = 5.0 V INO(OFF) -20 25 70 85 125 TEMPERATURE (C)
0.001
-55
Figure 9. Switch Leakage vs. Temperature
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NLAST44599
0 -20 -40 (dB) -60 -80 -100 0.01 VCC = 5.0 V TA = 25C 0 1.0 2.0 3.0 (dB) Off Isolation 4.0 5.0 6.0 7.0 8.0 9.0 100 200 10.0 0.01 VCC = 5.0 V TA = 25C 0.1 1 10 FREQUENCY (MHz) PHASE SHIFT Bandwidth (ON-RESPONSE) +15 +10 +5 0 -5 -10 -15 -20 -25 -30 -35 100 300 PHASE () 5
0.1
1 10 FREQUENCY (MHz)
Figure 10. Off-Channel Isolation
Figure 11. Typical Bandwidth and Phase Shift
30 25 20 TIME (ns) 15 10 5 0 2.5 tOFF (ns) tON (ns)
30 25 20 15 10 5 0 -55 tON tOFF VCC = 4.5 V
TIME (ns)
3
3.5
4
4.5
5
-40
25 Temperature (C)
85
125
VCC (VOLTS)
Figure 12. tON and tOFF vs. VCC at 255C
Figure 13. tON and tOFF vs. Temp
1 VINpp = 3.0 V VCC = 3.6 V THD + NOISE (%)
3.0 2.5 2.0 Q (pC) 1.5 1.0 0.5 0 VCC = 3 V VCC = 5 V
0.1 VINpp = 5.0 V VCC = 5.5 V
0.01
1
10 FREQUENCY (kHz)
100
-0.5 0
1
2 VCOM (V)
3
4
Figure 14. Total Harmonic Distortion Plus Noise vs. Frequency http://onsemi.com
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Figure 15. Charge Injection vs. COM Voltage
NLAST44599
100 10 1 ICC (nA) 0.1 0.01 0.001 0.0001 0.00001 -40 -20 0 VCC = 3.0 V 20 VCC = 5.0 V 20 60 80 100 120 0 0.0 1.0 VCC = 5.5 V 2.0 3.0 VIS (VDC) 4.0 5.0 6.0 RON (W) 60 VCC = 2.5 V 40 VCC = 3.0 V VCC = 4.0 V 100 VCC = 2.0 V 80
Temperature (C)
Figure 16. ICC vs. Temp, VCC = 3 V and 5 V
Figure 17. RON vs. VCC, Temp = 255C
100 90 80 70 RON (W) 50 40 30 20 10 0 0.0 85C 0.5 1.0 1.5 2.0 2.5 125C 25C -55C RON (W) 60
100 90 80 70 60 50 40 30 20 10 0 0.0 125C 0.5 -55C 85C 1.0 1.5 VIS (VDC) 2.0 2.5 3.0 25C
VIS (VDC)
Figure 18. RON vs Temp, VCC = 2.0 V
50 45 40 35 RON (W) RON (W) 30 25 20 15 10 5 0 0.0 -55C 0.5 125C 85C 25C 5 0 0.0 30 25 20 15 10
Figure 19. RON vs. Temp, VCC = 2.5 V
25C -55C
85C
125C
1.0
1.5
2.0
2.5
3.0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIS (VDC)
VIS (VDC)
Figure 20. RON vs. Temp, VCC = 3.0 V
Figure 21. RON vs. Temp, VCC = 4.5 V
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NLAST44599
25 20 15 25C 10 5 0 0.0 85C -55C 125C 25 20 125C RON (W) RON (W) 15 25C 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIS (VDC) 85C -55C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VIS (VDC)
Figure 22. RON vs. Temp, VCC = 5.0 V
Figure 23. RON vs. Temp, VCC = 5.5 V
DEVICE ORDERING INFORMATION
Device Nomenclature Device Order Number NLAST44599DT NLAST44599DTR2 NLAST44599MN NLAST44599MNG NLAST44599MNR2 NLAST44599MNR2G Circuit Indicator NL NL NL NL NL NL Technology AS AS AS AS AS AS Device Function 44599 44599 44599 44599 44599 44599 Package Suffix DT DT MN MN MN MN R2 R2 R2 Tape and Reel Suffix Package Type TSSOP-16* TSSOP-16* QFN-16 QFN-16 (Pb-Free) QFN-16 QFN-16 (Pb-Free) Shipping 96 Unit / Rail 2500 / Tape & Reel 124 Unit Rail 124 Unit Rail 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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NLAST44599
PACKAGE DIMENSIONS
QFN-16 MN SUFFIX CASE 485G-01 ISSUE B
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50
PIN 1 LOCATION
0.15 C 0.15 C
0.10 C
16 X
0.08 C
16X
L
NOTE 5 4
16X
K
1 16 16X 13
0.10 C A B 0.05 C
NOTE 3
III III III
TOP VIEW (A3) SIDE VIEW D2
5
E
A A1
C
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
e
0.575 0.022
8 EXPOSED PAD
EXPOSED PAD
9
E2
12
e
3.25 0.128
1.50 0.059
b BOTTOM VIEW 0.50 0.02
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NLAST44599
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 9
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE N-N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC -W- M 0_ 8_ 0_ 8_
D
G
H
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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NLAST44599/D

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